Article · Wikipedia archive · Last revised May 27, 2026

Ignite (microprocessor)

Ignite is a two stack, stack machine reduced instruction set computer (RISC) microprocessor architecture. The architecture was originally developed by Russell H. Fish III and Chuck H. Moore, Nanotronics, which was later acquired by Patriot Scientific Corporation. The processor is one of the few commercially produced microprocessors that use a stack-based computing model. Target applications for this unique architecture were mainly embedded devices and efficient implementation of virtual stack machines, such as the Java virtual machine or the stack machine underlying the Forth programming language. The product was unsuccessful in the market.

Last revised
May 27, 2026
Read time
≈ 1 min
Length
250 w
Citations
1
Source
Ignite
An Ignite Ia microprocessor
DesignerNanotronics, PTSC
Bits32-bit
Introduced1994 (1994)
DesignRISC
TypeStack machine
EndiannessBig
Registers
General-purpose52 (including stacks)

Ignite (formerly ShBoom and PSC 1000, stylized as IGNITE) is a two stack, stack machine reduced instruction set computer (RISC) microprocessor architecture.1 The architecture was originally developed by Russell H. Fish III and Chuck H. Moore, Nanotronics, which was later acquired by Patriot Scientific Corporation. The processor is one of the few commercially produced microprocessors that use a stack-based computing model. Target applications for this unique architecture were mainly embedded devices (due to the processor's low power use) and efficient implementation of virtual stack machines, such as the Java virtual machine or the stack machine underlying the Forth programming language. The product was unsuccessful in the market.

Notable features

Besides its unusual two stack-based architecture, the processor had several other valuable features:

  • Runs faster than the clock internally
  • Up to four instructions can be read on each instruction fetch, reducing memory-bandwidth requirements compared to typical 32 BIT RISC machines
  • This characteristic also allows looping on an instruction group (a micro-loop) without additional instruction fetches from memory
  • Single cycle (+ memory) sub-routine call
  • Implicit sub-routine return
  • Near Native speed Java interpretation with no JIT required, in approximately 20K bytes of code
  • Low power operation
References

References

  1. Shaw, G.W. (1999). PSC1000™ Microprocessor Reference Manual. Patriot Scientific Corporation. 99-037001.
Further reading

Further reading