Article · Wikipedia archive · Last revised Jul 12, 2026

VerilogCSP

In integrated circuit design, VerilogCSP is a set of macros added to Verilog HDL to support Communicating Sequential Processes (CSP) channel communications. These macros are intended to be used in designing digital asynchronous circuits. VerilogCSP also describes nonlinear pipelines and high-level channel timing properties, such as forward and backward latencies, minimum cycle time, and slack.

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Jul 12, 2026
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In integrated circuit design, VerilogCSP 1 is a set of macros added to Verilog HDL to support Communicating Sequential Processes (CSP) channel communications. These macros are intended to be used in designing digital asynchronous circuits. VerilogCSP also describes nonlinear pipelines and high-level channel timing properties, such as forward and backward latencies, minimum cycle time, and slack.

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References

  1. Saifhashemi, Arash; Peter Beerel (2005). "High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog". In Jan Broenink; Herman Roebbers; Johan Sunter; Peter Welch; David Wood (eds.). Communicating Process Architectures 2005. IOS Press. p. 275.